Semiconductor components comprising a logic circuit, such as are used in a CPU, for example, are often constructed with CMOS (complementary metal oxide semiconductor) gates. CMOS gates contain p-channel transistors arranged in an n-conductively doped well. The n-type wells are fixedly connected to the highest electrical potential provided (supply voltage VDD). The pn junction between the n-conductively doped well and the source-drain regions becomes non-conducting. Defined transistor properties are obtained as a result. Moreover, this arrangement prevents the well potential from falling below a value at which a so-called latch-up occurs that is to say a transition of the semiconductor component to a low-impedance state that can lead to an electrical short circuit and thus to thermal destruction of the component.
One problem in the case of semiconductor components for security-critical applications is also required safeguarding against light attacks by which functional disturbances of the component can be brought about or an undesirable external analysis of the circuit construction is intended to be made possible. There are already a number of proposals as to how a semiconductor component can be protected against light attacks.
In the case of light attacks, a distinction is made between global light attacks and local light attacks. In the case of global light attacks, the chip is exposed to light or ionizing radiation over a large area. This attack is not restricted to delimited regions. It is known that global light attacks can be detected by light sensors arranged in a scattered manner on the chip.
Local light attacks are locally highly delimited attacks on a semiconductor component and can be carried out by means of a laser, for example. By means of local light attacks, it is possible to change individual bits in sensitive regions. They generally require the chip housing to be opened and the circuit structure to be exposed. Local light attacks can be detected by means of a dual CPU (central processing unit) arrangement, for example.
US 2011/0043245 A1 discloses a semiconductor component including a parasitic activation structure for protection against light attacks, wherein the energy limit value for activating the parasitic structure is lower than the energy limit value for changing the status of a storage flip-flop of the semiconductor component. In this case, a current limiting circuit limits the current flowing in the semiconductor component.
The known measures are not only very complex and make the component considerably more expensive, but, as in the case of the dual CPU arrangement, may also result in an increase in the current consumption/demand and the area requirement. The additional area requirement of the components of a protective circuit readily exceeds the area available for the entire integrated circuit.